Method of production testing fuses and circuit for accomplishing such testing

ABSTRACT

Quality control testing of production current limiting fuses is achieved by subjecting the fuses to a minimum melt i2t (amp2 seconds) condition. The fuses to be tested are connected in an electrical circuit and subjected to a test current of given magnitude for one loop of a 60 hertz source.

United States Patent [191 Mikulecky et al.

111 3,772,590 [451 Nov. 13, 1973 METHOD OF PRODUCTION TESTING FUSES ANDCIRCUIT FOR ACCOMPLISHING SUCH TESTING Inventors: Harvey W. Mikulecky;William J.

Huber, both of Racine, Wis.

Assigneei McGraw-Edison Company,

Milwaukee, Wis.

Filed: May 24, 1972 Appl. No.: 256,381

US. Cl 324/28 R Int. Cl. H0lh 85/30 Field of Search 324/28 R, 158 R,

[56] References Cited UNITED STATES PATENTS 3,517,304 6/1970 Swartz324/28 R 3,489,926 1/1970 Adams et al 307/305 X Primary Examiner-AlfredE. Smith Attorney-John W. Michael et al.

13 Claims, 3 Drawing Figures A ll! METHOD OF PRODUCTION TESTING FUSESAND CIRCUIT FOR ACCOMPLISIIING SUCH TESTING BACKGROUND OF INVENTION Thisinvention relates to electrical testing of fuses, particularly those ofthe current limiting type.

The test method disclosed and claimed herein has particular applicationto current limiting fuses, but it will be appreciated that it may finduse beyond those specific types of fuses. The finally assembled fusesmust be electrically tested and also examined for structural flaws.Resistance and x-ray tests and visual checks have been proposed butthese are not particularly reliable. The fuses are housed in a tube,made of porcelain, fiberglass, or like, so that visual examination mustbe made before final assembly, but damage to the fuse element or faultyconnections can occur during final assembly. Visual examination forinternal structural flaws is impossible in the case of a totallyenclosed fuse and resistance and/r x-ray tests may miss some structuralflaws or defects.

SUMMARY OF INVENTION This invention is concerned with this problem ofadequately testing fuses electrically and detecting structural flaws andamong the general objects of this invention are to achieve reliabletesting and detection.

For more specific object of this invention is to closely approximatefield conditions in such testing.

For the achievement of these and other objects it is proposed that fuseratings be considered in terms of i t, where i is current and z is time.That is, the fuse is rated in terms of the amount of current it canwithstand for a given length of time without melting open. The magnitudeof i needed to melt a fuse open is referred to as the melt i whereasthat which the fuse can withstand without melting open is referred to asthe minimum melt i t. The minimum melt i t" is actually a preselectedpercentage of the melt i t sufficient to allow for reasonable toleranceand test variations.

The 1': test subjects the assembled fuse to a controlled current pulseand tests the fuse both electrically and structurally. The necessarymagnitude of test current for a given time is selected to provide theminimum melt i and the fuse is subjected to that electrical conditionwhich will uncover both electrical faults and structural flaws. The F!condition is a direct measure of the electrical capability of the fuse.Furthermore, any physical damage to the fuse element during manufacture,or error in material selection, which lowers the melt it, will also bedetected by subjecting the fuse to the minimum melt it. Defective fusesare thus readily detected, and are automatically rendered inoperable sothat they cannot get into service.

A 60 hertz electrical source is connected to the fuse being tested andcurrent in the fuse is controlled by providing conduction during onlyone loop (180) of the 60 hertz, i.e., a test shot of one loop duration.This provides a precisely measured duration of time for the test currentand the magnitude of current can then be readily computed to provide therequisite minimum melt it. The use of a 60 hertz source and only oneloop thereof, achieves the test under closely simulated fieldconditions. lt will be appreciated, however, that the circuit parameterscan be adjusted to use more than one loop and thereby subject the fuseto a number of test shots; these repeated one loop shots also simulatethe condition when a distribution transformer comes on the line.

This test procedure is extremely effective from an electrical standpointand will detect even the smallest structural flaw in a fully assembledfuse which would be capable of impairing fuse operation, and whichnormally cannot be detected by resistance or x-ray testing.

Other objects and advantages will be pointed out in, or be apparentfrom, the specification and claims, as will obvious modifications of theembodiment shown in the drawings, in which:

FIG. 1 is a circuit diagram illustrating the general concept of thisinvention;

FIG. 2 is a more specific circuit diagram illustrating a preferredembodiment; and

FIG. 3 is a plotting of voltage vs. time for the various controlcomponents of FIG. 2.

DESCRIPTION OF PREFERRED EMBODIMENT Before describing the test circuitryand the manner of carrying out the tests, it should be understood thatthe test arrangement can be used for testing any fuse structure. Forexample, it can be used for testing current limiting fuses of the typedisclosed and claimed in U.S. Pat.,No. 3,437,971 which is assigned tothe assignee of this application. That patent discloses and claims acurrent limiting fuse which, after final assembly, has the fusibleelement completely enclosed in an outer housing. The exact details ofthe fuse structure are not necessary to an understanding of thisinvention and hence a specific fuse construction will not be described,but reference is made to the aforementioned patent for a disclosure of atypical fuse structure should such a disclosure become necessary.

The general concept of the testing procedure will be described inconnection with the general showing of FIG. 1. An electrical source 10is connected through step down transformer 12 to a circuit branchincluding fuse 14 which is to be tested. Current in fuse 14 iscontrolled by SCR 16 which is in turn controlled by control circuit 18.The control circuit 18 is designed such that it will place the necessarygating signal on the gate of SCR 16 such that the SCR will be renderedconductive for one loop of the electrical source 10. More specifically,source 10 is a 60 hertz source and the voltage in primary 12 will alsobe 60 hertz and control circuit 18 is designed to turn SCR 16 on for oneloop of the 60 hertz. This invention is not limited to 60 hertz and canbe used with any frequency power source. Preferably, the SCR isautomatically turned off at the end of that loop when the source passesthrough the voltage, or current, zero. Thus the time of test current infuse 14 is precisely controlled to exactly one loop of the 60 hertzsource, i.e., 8.33 milliseconds. Resistance 20 is selected to providethe necessary current magnitude to provide the minimum melt f tcondition.

FIG. 2 depicts circuitry for carrying out the Ft test and for achievingsingle loop conduction for test purposes. Test fuse 22 is connected inseries with SCR 24, the latter controlling conduction in branch 26 ofthe test circuit. Variable resistance 28 is also included in the circuitto provide adjustment to achieve the desired test current magnitude.

Circuit branch 30 controls the conductive state of SCR 24 in a manner,now to be described, whereby SCR 24 is on for one loop of a 60 hertzsource. When switch 32 is closed, and assuming SCR 34 is to be off,

capacitor 38 is charged from DC. source 36. The conductive state of SCR34 is controlled by control circuit branch 40 including a transformer 42having its secondary 44 connected to the gate of SCR 34 through a switch46. Primary 48 is connected to A.C. source 50 which is in phase withvoltage 52 across SCR 24. To achieve this in-phase relationship source50 is preferably a tap off of source 52, both sources 50 and 52 being 60hertz. It will be noted that the voltage in secondary 44 will, becauseof this'relationship, be 180 out of phase with primary 48 andcorrespondingly the voltage on SCR 24 (i.e., source 52).

In operation, capacitor 38 is charged above the trigger voltage for SCR24 and, when charged, switch 32 is opened with capacitor 38 being readyto discharge through SCR 34 when the latter is rendered conductive,i.e., turned on. The discharge characteristics are determined by the RCnetwork formed by capacitor 38 and resistance 54. SCR 34 will be turnedon, assuming switch 46 is closed, when its gate is positive relative toits annode, the latter can be considered as continuously positivebecause of its connection to DC. source 36. This positive condition ofthe gate of SCR 34 occurs on alternate half cycles of source 50 and thusSCR 34 is turned on on alternate half cycles. However, because of the180 out of phase relationship between secondary 44 and source 52, whenSCR 34 is turned on allowing capacitor 38 to discharge through it andplace the necessary signal on the gate of SCR 24 to turn that SCR on thevoltage condition on the SCR is such that its annode is negativerelative to its cathode and it will not turn on. The discharge timeconstant of the RC network formed by capacitor 38 and resistance 54 isselected such that the discharge voltage of capacitor 38 remains abovethe trigger voltage of SCR 24 until the subsequent loop (one-half cycle)of source 52 is initiated. In the disclosed embodiment the dischargevoltage will decay below the trigger voltage before the end of that loopso that SCR 24 is turned off at end of that loop as a zero voltagecondition is crossed.

This out-of-phase relationship and single loop energization can perhapsbe better understood by reference to FIG. 3 wherein voltage is plottedagainst time, A plots voltage at the gate of SCR 34, B plots the voltageon SCR 24, D the trigger voltage of SCR 24, and C plots the dischargecurve for capacitor 38. As can be seen, when the signal on the gate ofSCR 34 is positive (curve or loop A) and capacitor 38 is discharging thevoltage across SCR 24 has a negative sense (graphically that loop of Bwhich would appear below loop A but has not been illustrated) but thecapacitor discharge voltage (curve C) remains above the SCR triggervoltage (curve D) as the voltage on SCR 24 transfers toa positive sense(loop or curve B). SCR 24 will be turned on at time T,. The capacitorvoltage decays to a valve below trigger voltage during the single loop Band SCR 24 will be turned off at T i.e., at the end of the single loop.This arrangement turns SCR 24 on precisely at the start of a single loopand turns it off precisely at the end of that loop giving an exactduration of time for the i test, on 60 hertz this equals 8.33milliseconds.

As can be seen from the foregoing specific description of the circuit ofFIG. 2, the time of the test current in test fuse 22 is preciselycontrolled, i.e., to a single loop of the 60 hertz source. This providesone test shot for the test fuse 22 such that if the fuse element hasbeen damaged or otherwise affected so that its minimum melt i is belowthe rated minimum melt i"! the fuse element will be melted open and thefuse is rejected. Providing a one shot test on a basis ofa 60 hertzsystem provides the electrical test under conditions which very closelyapproximate actual field conditions. That is the time of the test shotis similar to the abnormal conditions to which the fuse might besubjected in the field and, moreover, the test shot is relativelysymmetrical as might also be expected from a fault condition in thefield.

Although a single shot test situation has been described, it will beappreciated that repeated test shots can be achieved by adjusting the RCtime constant discharge for capacitor 38. In other words, the values ofresistance 54 and capacitor 38 can be selected to vary the slope ofcurve C as viewed in FIG. 3 such that the discharge voltage from thecapacitor does not fall below trigger voltage D as illustrated in FIG.3. More particularly, the curve could be extended so that it remainsabove the trigger voltage for subsequent positive phase loops of thevoltage on SCR 24 (curve B). Accordingly, the SCR 24 will still beturned off at the end of a given (loop B) because after passing throughcurrent 0, T the relative potential of the annode, gate and cathode ofSCR 24 would be improper for conduction during the negative phase of thevoltage curve for SCR 24.

However, on the next phase change from negative to positive in thevoltage on SCR 24, trigger voltage would still be on the gate of the SCRand it would be rendered conductive for a second single loop. Thus, theSCR can be rendered conductive on alternate loops of the voltage source52, i.e., on each positive phase thereof, and

will sujbect the fuse to repeated test shots. But each shot is againprecisely timed, i.e., one loop. These repeated test shots are similarto the condition which a fuse might encounter as a distributiontransformer is brought on line, and thus the characteristic ofsimulating field conditions which might be encountered in use ispreserved.

Although but one embodiment of the present invention has beenillustrated and described, it will be apparent to those skilled in theart that various changes and modifications may be made therein withoutdeparting from the spirit of the invention or from the scope of theappended claims.

We claim:

1. A test circuit for a fuse comprising in combination,

an electrical source,

means for connecting a fuse across said electrical source,

means for providing a test current of preselected magnitude in saidfuse,

switch means selectively operable to complete the circuit for said fuseand subject said fuse to said test current,

and means controlling the operation of said switch means and operatingsaid switch means to complete said circuit for a preselected time,

said duration of time and said current magnitude are characterized bybeing such as to provide a minimum melt i! for said fuse wherein i issaid test current and t is said preselected time.

2. The test circuit of claim 1 wherein said electrical source is a 60hertz source,

and said switch means is rendered conductive for one loop of said 60hertz.

3. The test circuit of claim 2 wherein said switch means is renderedoperative upon receipt of a control signal from said control meansduring one phase of said 60 hertz source, and said control means appliessaid control signal as said 60 hertz source is changing to said onephase and removes said control signal before said one phase againchanges so that said switch means is rendered conductive and said fuseis subjected to said test current for precisely one loop of said 60hertz. 4. The test circuit of claim 2 wherein said switch meanscomprises first electronic switch means characterized by being renderedconductive in response to receipt of a control signal during one phaseof said 60 hertz source, said control means includes a second electronicswitch means operative to provide said control signal but beingout-of-phase with said 60 hertz source to apply said control signal tosaid first elecr s switsh @2 2 PE PI to @516 her gur being in said onephase, and said control means further operative to maintain said controlsignal on said switch means until said 60 hertz source changes to saidone phase so that 1 said first electronic switch means is renderedconductive precisely as said 60 hertz source changes to said one phase.5. The test circuit of claim 2 wherein said switch means comprises afirst SCR connected across said 6( hertz source and in seri es with saidfuse, said SCR being capable of conduction when said 60 hertz source isin one phase, wherein said control means includes a second SCR connectedto the gate of said first SCR, including a source of potential connectedto and controlled by said second SCR, wherein said control means furtherincludes a control signal generating means connected to said second SCRto selectively turn on said second SCR and apply the necessary signal tosaid first SCR to render that SCR conductive, said control signalgenerating means being out-of-phase with said 60 hertz source to apply,said necessary signal prior to said 60 hertz source being in said onephase and maintaining said necessary signal until said 60 hertz sourcechanges to said one phase. 6. The test circuit of claim 5 wherein saidcontrol signal generating means includes a first A.C. source in phasewith said 60 hertz source, and means for shifting the phase of said A.C.source 180 relative to said 60 hertz source. 7. The test circuit ofclaim 6 wherein said phase shifting means comprises a transformer havingits primary connected to said first A.C. source and its secondaryconnected to the gate of said second SCR. 8. The test circuit of claim 7wherein said source of 5 potential comprises a capacitor capable ofcharging above the trigger voltage of said first SCR and having decaycharacteristics such that said trigger voltage is held until said 60hertz source changes to said one phase. I

9. The test circuit of claim 4 wherein said source of potentialcomprises a capacitor capable of charging above the trigger voltage ofsaid first SCR and having decay characteristics such that said triggervoltage is held until said 60 hertz source changes to said one phase.

10. The first circuit of claim 9 wherein the decay characteristics ofsaid capacitor are further characterized by said charge thereon decayingbelow said trigger voltage before said 60 hertz source changes from saidone phase.

11. The method of testing'a fuse comprising the steps of providing apreselected magnitude of current,

and selectively applying said current to said fuse for a preselectedduration of time,

wherein said duration of time and said current are selected to provide avalue of i t (i being said current and t being time) equal to theminimum melt i t for said fuse.

12. The method of claim 1 1 wherein said preselected duration of time isa single loop of a 60 hertz electrical source.

13. A test circuit for a fuse comprising in combination,

an A.C. voltage source for said fuse, switch means connected in circuitwith said fuse and said voltage source for controlling test current insaid fuse and having a non-conductive state and being turned on inresponse to a combination of said control signal and the phase of saidvoltage source, means for'providing said control signal to said switchmeans, and control means for operatively connecting said control signalproviding means to said switch means and being 180 out-of-phaseoperatively with said A.C. voltage source but capable of holding saidsignal on said switch means through a change in phase of said A.C.voltage source whereby said switch means applies test current to saidfuse at the start of the loop of said A.C. voltage source subsequent tothat loop in which said control means is operated.

1. A test circuit for a fuse comprising in combination, an electricalsource, means for connecting a fuse across said electrical source, meansfor providing a test current of preselected magnitude in said fuse,switch means selectively operable to complete the circuit for said fuseand subject said fuse to said test current, and means controlling theoperation of said switch means and operating said switch means tocomplete said circuit for a preselected time, said duration of time andsaid current magnitude are characterized by being such as to provide aminimum melt i2t for said fuse wherein i is said test current and t issaid preselected time.
 2. The test circuit of claim 1 wherein saidelectrical source is a 60 hertz source, and said switch means isrendered conductive for one loop of said 60 hertz.
 3. The test circuitof claim 2 wherein said switch means is rendered operative upon receiptof a control signal from said control means during one phase of said 60hertz source, and said control means applies said control signal as said60 hertz source is changing to said one phase and removes said controlsignal before said one phase again changes so that said switch means isrendered conductive and said fuse is subjected to said test current forprecisely one loop of said 60 hertz.
 4. The test circuit of claim 2wherein said switch means comprises first electronic switch meanscharacterized by being rendered conductive in response to receipt of acontrol signal during one phase of said 60 hertz source, said controlmeans includes a second electronic switch means operative to providesaid control signal but being out-of-phase with said 60 hertz source toapply said control signal to said first electronic switch Means prior tosaid 60 hertz source being in said one phase, and said control meansfurther operative to maintain said control signal on said switch meansuntil said 60 hertz source changes to said one phase so that said firstelectronic switch means is rendered conductive precisely as said 60hertz source changes to said one phase.
 5. The test circuit of claim 2wherein said switch means comprises a first SCR connected across said 60hertz source and in series with said fuse, said SCR being capable ofconduction when said 60 hertz source is in one phase, wherein saidcontrol means includes a second SCR connected to the gate of said firstSCR, including a source of potential connected to and controlled by saidsecond SCR, wherein said control means further includes a control signalgenerating means connected to said second SCR to selectively turn''''on'''' said second SCR and apply the necessary signal to said firstSCR to render that SCR conductive, said control signal generating meansbeing out-of-phase with said 60 hertz source to apply said necessarysignal prior to said 60 hertz source being in said one phase andmaintaining said necessary signal until said 60 hertz source changes tosaid one phase.
 6. The test circuit of claim 5 wherein said controlsignal generating means includes a first A.C. source in phase with said60 hertz source, and means for shifting the phase of said A.C. source180* relative to said 60 hertz source.
 7. The test circuit of claim 6wherein said phase shifting means comprises a transformer having itsprimary connected to said first A.C. source and its secondary connectedto the gate of said second SCR.
 8. The test circuit of claim 7 whereinsaid source of potential comprises a capacitor capable of charging abovethe trigger voltage of said first SCR and having decay characteristicssuch that said trigger voltage is held until said 60 hertz sourcechanges to said one phase.
 9. The test circuit of claim 4 wherein saidsource of potential comprises a capacitor capable of charging above thetrigger voltage of said first SCR and having decay characteristics suchthat said trigger voltage is held until said 60 hertz source changes tosaid one phase.
 10. The first circuit of claim 9 wherein the decaycharacteristics of said capacitor are further characterized by saidcharge thereon decaying below said trigger voltage before said 60 hertzsource changes from said one phase.
 11. The method of testing a fusecomprising the steps of providing a preselected magnitude of current,and selectively applying said current to said fuse for a preselectedduration of time, wherein said duration of time and said current areselected to provide a value of i2t (i being said current and t beingtime) equal to the minimum melt i2t for said fuse.
 12. The method ofclaim 11 wherein said preselected duration of time is a single loop of a60 hertz electrical source.
 13. A test circuit for a fuse comprising incombination, an A.C. voltage source for said fuse, switch meansconnected in circuit with said fuse and said voltage source forcontrolling test current in said fuse and having a non-conductive stateand being turned ''''on'''' in response to a combination of said controlsignal and the phase of said voltage source, means for providing saidcontrol signal to said switch means, and control means for operativelyconnecting said control signal providing means to said switch means andbeing 180* out-of-phase operatively with said A.C. voltage source butcapable of holding said signal on said switch means through a change inphase of said A.C. voltage source whereby said switch means applies testcurrent to said fuse at the start of the loop of said A.C. voltagesource subsequent to that loop in which Said control means is operated.